1. Technical Field
The present disclosure relates to a time-interleaved analog-to-digital (AD) converter.
2. Description of the Related Art
Time-interleaved analog-to-digital (AD) converters have various architectures and are used in ways dependent on specifications thereof, which include the resolution, sampling frequency, and power consumption. Since, among such AD converters, an AD converter that operates at high-speed sampling frequencies higher than 1 GHz is difficult to be implemented with a single AD converter, a time-interleaved AD converter is often used.
The time-interleaved AD converter has an architecture in which N AD converters referred to as “channel AD converters” hereinafter, N representing an integer equal to or larger than two, are arranged and operational clock signals with phases that are evenly shifted are respectively input to the N AD converters and after the AD conversion, output data are coupled. Thus, the operational clock frequency of each channel AD converter can be caused to be 1/N times as high as the sampling frequency. As a result, even a high-speed AD converter whose sampling frequency is higher than 1 GHz can be implemented.
In the time-interleaved AD converter, however, various errors occur, which are caused by unevenness in or mismatch among elements that make up each channel AD converter. Particularly, a timing error, which is hereinafter referred to as a “timing skew”, of a clock signal caused in sampling is a major issue because such an error deteriorates the precision of the AD conversion, that is, the signal-to-noise (SN) ratio.
The timing skew is caused by unevenness in or mismatch of switches or capacitors in the sampling circuits of the channel AD converters, or a difference in paths from a clock generation circuit to the channel AD converters. The AD conversion result obtained when a timing skew is caused includes a spurious signal that occurs on an output spectrum thereof. Particularly when a high-frequency signal is input, a large AD conversion error caused by the timing skew appears and thus, the SN ratio is largely decreased.
Many methods have been proposed so as to correct a timing skew that occurs in a time-interleaved AD converter. Such methods include a method in which a reference signal is supplied to an input signal and a phase of a clock signal of each channel AD converter is adjusted using a variable delay circuit or the like. This method can correct a timing skew with reliability and in a short time. The proposed methods include a method in which a timing skew is estimated by inputting a signal generated by a digital-to-analog converter, referred to as a DAC hereinafter, as a reference signal while shifting the phase of the signal, and by detecting an edge of the signal (see, for example, V. H.-C. Chen and L. Pileggi, “A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI”, IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2891-2901, December 2014), The proposed methods also include a method in which a ramp wave is input as a reference signal and delay of a clock signal of each channel AD converter is adjusted so that the AD conversion results of the channel AD converters are the same as one another (see, for example, Z. Liu, K. Honda, and S. Kawahito, “A New Calibration Method for Sampling Clock Skew in Time-interleaved ADC”, IEEE International Instrumentation and Measurement Technology Conference, May 2008).